Controlling Gate Formation for High Density Cell Layout

ABSTRACT

Methods of forming a semiconductor structure and the semiconductor structure are disclosed. In one embodiment, a semiconductor structure includes a substrate having a first active region, a second active region, and an insulating region separating the first and the second active regions. The structure further includes a vertical gate structure extending over the first and the second active regions and the insulating region, and a horizontal gate structure extending over the insulating region between the first and the second active regions.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No.12/897,559 filed on Oct. 4, 2010, now U.S. Pat. No. 9,070,623, andentitled “Controlling Gate Formation for High Density Cell Layout”,which is a continuation-in-part of U.S. patent application Ser. No.12/193,538 filed Aug. 18, 2008, now U.S. Pat. No. 8,105,929, andentitled “Gate Control and Endcap Improvement”, which is a continuationof U.S. application Ser. No. 11/012,414 filed on Dec. 15, 2004, now U.S.Pat. No. 7,432,179, and entitled “Controlling Gate Formation By Removingdummy Gate Structures”, the disclosures of which are incorporated hereinby reference in their entirety and for all purposes.

BACKGROUND

This invention relates to semiconductor devices, specifically to thegate critical dimension control and endcap improvement through use ofdummy patterns.

The existence of pattern effect in films has been well known. There is aproblem that a “micro-loading effect” occurs due to a difference inpattern density and degrades the uniformity of pattern sizes. Themicro-loading effect pertains to a phenomenon occurring uponsimultaneously etching or polishing a pattern of a higher density and apattern of a lower density. Due to a difference in the etching/polishingrate of a film from one location to another, the amount of reactionproduced by the etching/polishing becomes locally dense or sparse, andthe convection of a large amount of reaction products by etching with alow volatility causes a non-uniformity in the etching rate. Largevariations in effective pattern density have been shown to result insignificant and undesirable effects such as pattern dimension deviationand thickness variation.

To counteract this effect, a layout design step known as dummy fill,where the circuit layout is modified and dummy patterns are added tolocations with low pattern density, was developed. The adding of dummypatterns helps to achieve uniform effective pattern density across thewafer, therefore avoiding problems.

Conventionally, such dummy patterns are left in place. In the case dummypatterns are conductive, they form parasitic capacitance with theinterlayer metal wiring. The parasitic capacitance contributes to the RCtime delay due to charging and discharging time. The scaling scheme ofinterlayer dielectrics (ILD) and higher operation frequency for advancedprocesses will cause severe performance degradation due to unwantedparasitic capacitance. At the present stage of development of theintegrated circuit art, there is an increasing demand in the field ofdigital integrated circuits for faster switching circuits. As theswitching demands of the integrated circuits go into higher frequency,the slowing effect produced by parasitic capacitance becomes anincreasing problem.

Since dummy patterns are not removed, they cannot be formed in an activeregion, or oxide defined (OD) region. Leftover dummy patterns not onlyincrease parasitic capacitance and degrade device performance, but alsoaffect the subsequent processes. One of the conventional solutions is toplace dummy patterns surrounding, but not in, the active regions. Notbeing able to be placed in desired regions, the effect of the dummypatterns is significantly limited. Such an arrangement also increasesthe difficulty of fine-tuning the dummy patterns. There were alsoefforts made to put dummy patterns into dummy active regions, or regionshaving neither an oxide nor an active device. However, the results havegenerally not proven satisfactory.

There is another effect that also affects the semiconductor process.When two devices are too close to each other, “optical proximityeffects” occur. Optical proximity effects are due to light diffractionand interference between closely spaced features on the reticleresulting in the widths of lines in the lithographic image beingaffected by other nearby features. One component of the proximity effectis optical interaction among neighboring features; other componentsarise from similar mechanisms in the resist and etch processes. Thus,under the present restricted design rule (RDR) environment, when aspecial layout design of polysilicon (“poly”) gates includes poly gatesdisposed in vertical and horizontal directions (from a top viewperspective), an area penalty is needed to avoid undesirable sideeffects in lithography, process, and device. For example, as shown inFIGS. 15 and 17, the minimum spacing between the tip of a vertical polyline endcap 87 and an adjacent horizontal poly line 80 c has typicallybeen a minimum of about 100 nm for lithography to be used to form asatisfactory poly line. In another example, as further shown in FIGS. 15and 17, a poly endcap 87 has been required to extend a minimum of 80 nmto also avoid optical proximity effects.

The micro-loading and proximity effects affect the gate formation ofmetal-oxide-semiconductor (MOS) devices. The critical dimension, or thegate length of a MOS device, may deviate significantly from design. Forexample, if an 80 nm gate length is desired, when the critical dimensionof a MOS device in a dense device area is on target at 80 nm, thecritical dimension of a MOS device in an isolated device area may reacharound 110 nm, or 30 nm more than the target value in certain cases.Also the deviations for nMOS and pMOS gates are different, causing N/Pratio mismatching and complicating circuit design. Furthermore, thespacing limitations for vertical and horizontal poly lines mentionedabove make improving total gate density difficult.

Lack of process control in gate formation also causes endcap problems.FIG. 1 illustrates a conventional layout comprising two MOS devices.Gate 2 and active region 6 form a first device 8. Gate 4 and activeregion 7 form a second device 5. Gates 2 and 4 have endcaps 9 and 11respectively, extending outside active regions 6 and 7. Due to the microloading or proximity effects, endcaps 9 and 11 may be longer or shorterthan designed. When endcaps 9 and 11 are longer than designed,polysilicon (“poly”) gates 2 and 4 may be shorted, causing devicefailure. Conversely, problems may also occur if endcaps 9 and 11 areshorter than designed, as shown in FIG. 2. If endcap 9 or 11 is recessedinto the active region 6 or 7, it cannot effectively control the channelof the device and shut off the MOS device. As a consequence, asignificant leakage current may exist between the source and drain ofdevices 8 and 5.

SUMMARY

The present disclosure provides for many different embodiments. One ofthe broader forms of the present disclosure involves a method offabricating a semiconductor device. The method includes forming a gatedielectric layer over a substrate, forming a gate electrode layer overthe gate dielectric layer, and etching the gate electrode layer and thegate dielectric layer to form a horizontal gate structure and a verticalgate structure, wherein the horizontal gate structure and the verticalgate structure are connected by an interconnection portion. The methodfurther includes forming a photoresist covering the horizontal gatestructure and the vertical gate structure, with the photoresist having agap exposing the interconnection portion between the horizontal gatestructure and the vertical gate structure, and then etching theinterconnection portion.

Another of the broader forms of the present disclosure involves anothermethod of fabricating a semiconductor device. The method includesproviding a semiconductor substrate comprising: a first active region; asecond active region; and an insulating region separating the first andthe second active regions. The method further includes forming avertical gate structure extending over the first and the second activeregions and the insulating region, and forming a horizontal gatestructure extending over the insulating region between the first and thesecond active regions, wherein the horizontal gate structure and thevertical gate structure are connected by an interconnection portion. Aphotoresist having a first portion and a second portion is then formed,wherein the first portion of the photoresist covers a portion of thevertical gate structure, and the second portion of the photoresistcovers the horizontal gate structure, wherein the first and the secondportions of the photoresist have a gap exposing the interconnectionportion directly over the insulating region. The interconnection portionis then etched.

Another of the broader forms of the present disclosure involves asemiconductor structure. The semiconductor structure includes asubstrate having a first active region, a second active region, and aninsulating region separating the first and the second active regions.The structure further includes a vertical gate structure extending overthe first and the second active regions and the insulating region, and ahorizontal gate structure extending over the insulating region betweenthe first and the second active regions, wherein the horizontal gatestructure and the vertical gate structure have a gap of about 80 nmtherebetween directly over the insulating region.

By using embodiments of the present invention, the critical dimensionsof the MOS devices are controlled. Bridging and line end shortening areavoided. Due to more accurate device dimensions with respect to design,N/P ratios are more controllable without the need for complicated finetune techniques such as optical proximity correction (OPC). Therefore,the overall chip speed and performance are improved. Also, the spacinglimitations of adjacent vertical and horizontal polysilicon lines arereduced and the total gate density may be improved.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isemphasized that, in accordance with the standard practice in theindustry, various features are not drawn to scale. In fact, thedimensions of the various features may be arbitrarily increased orreduced for clarity of discussion. Reference is now made to thefollowing descriptions taken in conjunction with the accompanyingdrawings, in which:

FIG. 1 illustrates a top view of a conventional semiconductor structurehaving endcaps of MOS devices next to each other;

FIG. 2 illustrates a top view of a conventional semiconductor structurehaving endcaps of MOS devices next to each other, the endcaps arerecessed into the active regions;

FIGS. 3 through 9 are cross-sectional views and top views ofintermediate stages in the manufacture of a MOS transistor embodiment;and

FIGS. 10 through 12 are top views of intermediate stages in themanufacture of another MOS transistor embodiment, wherein endcaps of twoMOS devices are next to each other.

FIGS. 13A-13C illustrate top views of intermediate stages in themanufacture of a semiconductor structure.

FIGS. 14A-14C illustrate top views of intermediate stages in themanufacture of another semiconductor structure.

FIGS. 15 and 16 illustrate top views of a conventional semiconductorstructure and a semiconductor structure having vertical and horizontalgate structures in accordance with aspects of the present disclosure,respectively.

FIGS. 17 and 18 illustrate top views of another conventionalsemiconductor structure and another semiconductor structure havingvertical and horizontal gate structures in accordance with aspects ofthe present disclosure, respectively.

FIGS. 19 and 20 illustrate top views of a conventional semiconductorstructure and a semiconductor structure including a contact inaccordance with aspects of the present disclosure, respectively.

FIG. 21 is a flowchart illustrating a method of fabricating asemiconductor structure with a high density gate layout according tovarious aspects of the present disclosure.

DETAILED DESCRIPTION

It is to be understood that the following disclosure provides manydifferent embodiments, or examples, for implementing different featuresof the invention. Specific examples of components and arrangements aredescribed below to simplify the present disclosure. These are, ofcourse, merely examples and are not intended to be limiting. Moreover,the formation of a first feature over or on a second feature in thedescription that follows may include embodiments in which the first andsecond features are formed in direct contact, and may also includeembodiments in which additional features may be formed interposing thefirst and second features, such that the first and second features maynot be in direct contact. Various features may be arbitrarily drawn indifferent scales for simplicity and clarity. In addition, although thepresent disclosure provides examples of a damascene process and a “gatelast” metal gate process, one skilled in the art may recognizeapplicability to other processes and/or use of other materials.

The making and using of the present embodiments are discussed in detailbelow. It should be appreciated, however, that the present inventionprovides many applicable inventive concepts that can be embodied in awide variety of specific contexts. The specific embodiments discussedare merely illustrative of specific ways to make and use the invention,and do not limit the scope of the invention.

For the embodiments illustrated in FIGS. 3 through 12, like referencenumbers may designate like elements throughout the various views andillustrative embodiments. Each figure number may be followed by a letterA or B, where A indicates that the figure is a cross sectional view andB indicates a corresponding top view of the figure whose numbers have an“A” as suffix.

FIGS. 3 through 9 are cross-sectional views and top views ofintermediate stages in the manufacture of a gate structure of a MOStransistor embodiment. FIG. 3 illustrates stack layers formed on asubstrate 10. Substrate 10 comprises active regions on which MOS devicescan be formed. Typically, the boundaries of active regions are definedby oxides such as shallow trench isolations. Depending on where anactive region is located, a non-oxide region may be referred as eitheran active region, which has active devices formed therein, or a dummyactive region, which has no active devices formed therein. A gatedielectric layer 12 is formed over the substrate 10. Gate dielectriclayer 12 may be formed of thermal oxidation or other methods. Gatedielectric layer 12 may be comprised of SiO₂, oxynitride, nitride,and/or high-k materials. A gate electrode layer 14 is formed on the gatedielectric layer 12. In one example, gate electrode 14 is comprised ofpolysilicon, although it may also be metal or metal compound comprisingtitanium, tungsten, cobalt, aluminum, nickel or combinations thereof.For the case gate electrode 14 is comprised of polysilicon, silane(SiH₄), di-silane (Si₂H₆), or di-chlorosilane (SiCl₂H₄) may be used as achemical gas in a CVD process to form the poly layer in one example.Alternatively, an amorphous silicon layer may optionally be formedinstead of the polysilicon layer.

Substrate 10 may be comprised of silicon material or alternatively mayinclude silicon germanium, gallium arsenic, or other suitablesemiconductor materials. The substrate 10 may further include dopedregions such as a P-well and/or an N-well (not shown). The substrate 10may also include other features such as a buried layer, and/or anepitaxy layer. Furthermore, the substrate 10 may be a semiconductor oninsulator such as silicon on insulator (SOI). In other embodiments, thesemiconductor substrate 10 may include a doped epitaxy layer, a gradientsemiconductor layer, and/or may further include a semiconductor layeroverlying another semiconductor layer of a different type, such as asilicon layer on a silicon germanium layer. In other examples, acompound semiconductor substrate may include a multilayer siliconstructure or a silicon substrate may include a multilayer compoundsemiconductor structure. The active region may be configured as an NMOSdevice (e.g., nFET) or a PMOS device (e.g., pFET) in one example.

FIG. 3 also illustrates a photoresist 19 formed over the electrode 14.Since the gate dimensions are critical, an anti-reflective coating (ARC)13 may be formed. FIG. 4 illustrates a bottom anti-reflective coating(BARC) 13 that is formed under the photoresist 19. In alternativeembodiments, a top anti-reflective coating (TARC) may also be formed ontop of the photoresist 19. ARC 13 absorbs light and provides ultimatecritical dimension control. The material of the BARC 13 depends on thematerial of the photoresist 19 and may be organic materials or inorganicmaterials, such as SiO_(x)N_(y) and SiN formed of low-pressure chemicalvapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition(PECVD), and oxide. A person skilled in the art will recognize the rightcombination of the photoresist 19 and suitable ARC 13 materials. BARC 13can be applied using a spin-on technique or by deposit in a gas chamberin one example.

FIG. 4 illustrates formation of gate structure 16 and dummy patterns 18.Openings 15 are formed in photoresist 19 and BARC 13. The processsuitable for forming such openings depends on the materials of thephotoresist 19 and BARC 13. In this embodiment, BARC 13 is organic anddeveloper soluble, thus photoresist 19 and BARC 13 can be exposed anddeveloped in one process. In other embodiments, either BARC 13 isinorganic or developer insoluble, and a two-step process is performed.The photoresist 19 is exposed and developed first, and BARC 13 is thenremoved from the openings in the photoresist 19 and thus openings 15 areformed. Exposed gate electrode layer 14 and dielectric layer 12 are thenetched through the openings 15, forming gate stack 16 and dummy patterns18. Both gate 16 and dummy patterns 18 include a gate oxide layer 12, agate electrode 14 and a BARC 13. The method of etching gate electrodelayer 14 and dielectric layer 12 is well known in the art.

Photoresist 19 is then stripped or etched, forming a structure shown inFIG. 5A. FIG. 5B illustrates a top view of the structure in FIG. 5A. Atleast one of the dummy patterns 18 has a portion formed on the activeregion 20. Since the dummy patterns 18 can be formed in the activeregion, it is significantly easier to arrange the dummy patterns so thatthe effective device density is substantially uniform throughout a chip.The results have shown that the micro-loading effect is effectivelyreduced by the embodiment. Typically, in the after developmentinspection, the deviation of the critical dimension is less than about 2nm, which means when the target critical dimension is 80 nm, theresulting critical dimension is between about 78 nm to about 82 nm.

For clarity, only two dummy patterns 18 are shown in FIG. 5B. In anactual design, the number of dummy patterns and the spacing betweendummy patterns will change and can be generated and fine tuned by adummy utility system. Since nMOS and pMOS devices react differently tomicro-loading effects, the spacing between the dummy patterns in an nMOSregion and a pMOS region can be different. Non-uniform spacing canfurther increase the accuracy of the critical dimension and lower thedeviations.

The embodiment discussed above illustrates one of the methods forforming gate structures. Other methods may also be used in alternativeembodiments. If lithography, etching, or CMP are involved, micro-loadingeffects occur and dummy patterns are formed. In one embodiment, dummypatterns are formed of the same material as the gate electrode.

Dummy patterns 18 are then removed since they affect the subsequentprocesses and otherwise may cause device performance degradation. FIG.6A illustrates a photoresist 22 formed covering the gate structure 16.In some cases, it may be desired that photoresist 22 extends beyond gatestructure 16 for between about 10 nm and about 150 nm so that it isguaranteed that the gate structure 16 is completely covered. The purposeof the photoresist 22 is to protect the gate structure when dummypatterns 18 are removed. Therefore the dimension and alignment ofphotoresist 22 are not critical as long as it protects gate structure 16without covering dummy patterns 18. FIG. 6B illustrates a top view ofthe structure illustrated in FIG. 6A. As shown, gate structure 16 iscovered completely and dummy patterns 18 are left uncovered.

Dummy patterns 18 are then etched. Since the gate structure 16 iscompletely protected by photoresist 22, it is not etched and thedimensions created in the previous forming steps are preserved.

FIG. 7A illustrates the gate structure after the photoresist 22 isremoved. FIG. 7B illustrates a top view of FIG. 7A. The BARC layer 13 isstripped after the device gate pattern is formed. Remaining elements ofthe MOS devices such as gate spacers, source and drain, etc. are formedusing known methods, as shown in FIG. 8. A pair of spacers 23 is formedalong the sidewalls of the gate dielectric 12 and gate electrode 14.Spacers 23 serve as self-aligning masks for subsequent source/drainformation steps, as described below. The spacers 23 may be formed bywell-known methods such as blanket or selectively depositing adielectric layer over regions including substrate 10 and gate structure16, then anisotropically etching to remove the dielectric from thehorizontal surfaces and leaving spacers 23. In this embodiment, dopingof the regions of substrate 10 on the side of spacers 23 may beperformed to form part or the entire transistor source and drain regions24. In other embodiments, other methods of forming source and drainregions 24 may be used.

FIG. 9 illustrates formation of a silicide 26 and an etch stop layer(ESL) 28. Silicide 26 is formed over source and drain regions 24 and inone embodiment over gate electrode 14 as well. In one embodiment,silicide 26 is a metal silicide formed by first depositing a thin layerof metal, such as titanium, cobalt, nickel, tungsten, or the like, overthe device, including the exposed surfaces of source and drain regions24 and gate electrode 14. The device is then heated, which causes thesilicide reaction to occur wherever the metal is in contact with thesilicon. After reaction, a layer of metal nitride is formed betweensilicide and metal. The un-reacted metal is selectively removed throughthe use of an etchant that does not attack the silicide, SiO₂ andsilicon substrate.

An etch stop layer (ESL) 28 is next blanket deposited over the device.ESL 28 may be formed using low-pressure chemical vapor deposition(LPCVD), but other CVD methods, such as plasma enhanced chemical vapordeposition (PECVD), and thermal CVD may also be used.

FIGS. 10 through 12 illustrate another embodiment of the presentinvention. In some situations that the gate endcaps of two devices areclosely located, as shown in FIG. 1, problems such as bridging and polyline end shortening may occur, causing device failure or degradation.Therefore, gate endcap dimensions need to be controlled carefully. Asnoted previously, prior gate endcaps were required to extend a minimumof 80 nm to avoid optical proximity effects.

FIG. 10 illustrates a top view of this embodiment after the gatestructures 42 and 43 and dummy patterns 40 are formed. The method forforming gates 42 and 43 and dummy patterns 40 has been described withreference to FIGS. 3 through 5 and will not be repeated in the presentembodiment. A gate structure 42 for MOS device 41 is formed with atleast a portion on a first active region 46. A gate structure 43 for MOSdevice 51 is formed with at least a portion on a second active region48. The first and second active regions may actually be one activeregion or separated regions. Gate structures 42 and 43 areinterconnected at point 44. As has been discussed, the introduction ofdummy patterns into active regions improves the process so that thecritical dimensions of the gates 42 and 43 are more closely on target.MOS devices 41 and 51 can be an nMOS-pMOS pair, two nMOS or two pMOS, orother combinations. Since dummy patterns 40 can be formed in activeregions 46 and 48, device densities are more uniform and the deviationof the critical dimensions of gates 42 and 43 is controlled better.

FIG. 11 illustrates a photoresist 50 formed protecting the gatestructures 42 and 43. Similar to the previously discussed embodiment, itmay be desirable that photoresist 50 extends beyond gates 42 and 43 forbetween about 10 nm and about 150 nm so that it is guaranteed that thegates 42 and 43 are completely covered. A gap 47 is formed between thephotoresist covering gates 42 and 43. In one embodiment, gap 47 has awidth D of greater than about 50 nm, and in yet another embodimentbetween about 50 nm and about 500 nm, although the width D is a designconsideration and can be changed according to the layout. In order toprevent over-etching through the gap 47 in the subsequent process stepscausing gate ends recessing back into active regions 46 and 48, it maybe desired that the photoresist 50 extends beyond active regions 46 and48 for a distance W_(E) of more than about 50 nm, and in anotherembodiment, more than about 200 nm.

Dummy patterns 40 are then etched and photoresist 50 is removed. Theresulting structure after the photoresist 50 is removed is illustratedin FIG. 12. The connecting portion unprotected by the photoresist 50 isalso etched and gates 42 and 43 are disconnected. By using thisembodiment of the present invention, the endcaps 54 and 56 arecontrolled so that no bridging or end shortening occurs due tolithography and etching.

The remaining elements of the MOS device such as spacers, source/drain,etc, are then formed. The forming process has been discussed in previousembodiments and thus will not be repeated.

By using embodiments of the present invention, the critical dimensionsof the MOS devices are controlled. Typically, in an 80 nm criticaldimension device, the deviation of the critical dimension is less thanabout 2 nm. Bridging and line end shortening are avoided. Due to moreaccurate dimension control with respect to design, N/P ratios are morecontrollable without using complicated fine tune techniques such as OPCand LPE. The overall chip speed and performance are improved. Althoughthe embodiments of the present invention only discusses the process ofnormal MOS devices, other MOS devices such as double gate transistorsand lateral diffusion MOS can also benefit.

Referring now to FIGS. 13A-13C, top views are illustrated ofintermediate stages in the manufacture of a semiconductor structurehaving vertical and horizontal gate structures in a high density layout.FIG. 13A illustrates a top view of a gate structure 60 includingvertical gate structures 60 a and 60 b and horizontal gate structures 60c and 60 d. Portions of vertical gate structures 60 a and 60 b areformed over active regions 62 and 64, Horizontal gate structures 60 cand 60 d are formed over insulating regions. Dummy patterns (not shown)may also be formed in active and insulating regions. The dummy patternsmay have uniform or non-uniform spacing and may be comprised of the samematerial as the gate structures. An example method for forming gatestructure 60 and dummy patterns has been described above with referenceto FIGS. 3 through 5 and will not be repeated in the present embodiment.However, various layer deposition, photolithography, and etch techniquesmay be used to form gate structure 60. As will be noticed, vertical gatestructures 60 a, 60 b and horizontal gate structures 60 c, 60 d formseveral sections of an “H” shaped gate structure 60 with an overbar 60d. It will be further noticed that vertical gate structures 60 a, 60 band horizontal gate structures 60 c, 60 d can form several “T” and “L”shaped parts of the gate structure 60. For example, in this embodiment,horizontal gate structure 60 d and vertical gate structure 60 a form a“T” shaped part of gate structure 60. The horizontal gate structure 60 dand vertical gate structure 60 a are interconnected by aninterconnection portion 65, which will be later etched as furtherdescribed below. An example of an “L” shaped part of gate structure 60is formed by horizontal gate structure 60 d and vertical gate structure60 b. Although the interconnection portion 65 is described in thisembodiment, gate structure 60 may be considered to have aninterconnection portion at any section between a horizontal gatestructure and a vertical gate structure which is desired to be etched.

FIG. 13B illustrates a photoresist 66 formed over gate structure 60protecting the vertical and horizontal gate structures but exposing theinterconnection portion 65 through a photoresist gap 68 in thephotoresist 66. Similar to the previously discussed embodiment,photoresist 66 may extend beyond parts of gate structure 60 for betweenabout 10 nm and about 150 nm so that parts of the gate structure arecompletely covered. Gap 68 is formed in the photoresist 66 over theinterconnection portion 65. In one embodiment, gap 68 has a width “y”between about 65 nm and about 95 nm (as shown by a gate gap 69 in gatestructure 60 in FIG. 13C), although the width y of photoresist gap 68 isa design consideration and can be changed according to the layout. Thus,in one aspect, the width y between a horizontal gate structure and avertical gate structure end is between about 65 nm and about 95 nm, andin another aspect width y is greater than about 80 nm and less than 100nm. In order to prevent over-etching through the photoresist gap 68 inthe subsequent process steps causing gate ends to recess back intoactive region 62, photoresist 66 extends beyond active region 62 for adistance between about 40 nm and about 60 nm in one aspect (as shown byendcap 67 in FIG. 13C). The patterned photoresist 66 may be formed byphotolithography, immersion lithography, ion-beam writing, or othersuitable techniques. For example, the photolithography process mayinclude spin-coating, soft-baking, exposure, post-baking, developing,rinsing, drying, and other suitable processes.

Dummy patterns are then etched and photoresist 66 is removed. Theresulting gate structure after the photoresist 66 is removed isillustrated in FIG. 13C. The interconnection portion 65 unprotected bythe photoresist 66 is also etched and removed, thereby forming endcap 67extending a distance “z” between about 40 nm and about 60 nm aboveactive region 62, and forming gate gap 69 having a minimum width ybetween about 65 nm and about 95 nm. Thus, in one example, a distance“x” between a bottom edge of the horizontal gate structure 60 d and atop edge of active region 62 of the substrate is between about 105 nmand about 155 nm, which is reduced from the conventional spacingrequirement of 180 nm. By using this embodiment of the presentinvention, the minimum extension of endcaps and the minimum spacingbetween vertical and horizontal gate lines are controlled and optimizedto reduce the area constraints conventionally required of vertical andhorizontal gate lines, thus improving gate line density while alsoimproving device performance and leakage uniformity control.

The dummy patterns and the interconnection portion may be removed by adry etching, wet etching, or combination dry and wet etching process.For example, a wet etching process may include exposure to a hydroxidecontaining solution (e.g., ammonium hydroxide), de-ionized water, and/orother suitable etchant solutions. Etching the poly layer may beperformed using HBr, CF₄, Cl₂, O₂ or HeO₂ at a temperature of about 0°C.-100° C. Furthermore, the dummy patterns and the interconnectionportion may be removed in a single-step etching process or multiple-stepetching process. It is understood that other etching chemicals may beused for selectively removing the dummy dielectric and dummy poly gate.

The remaining elements of the MOS device such as spacers, source/drain,etc, are then formed. The forming process has been discussed in previousembodiments and thus will not be repeated.

FIGS. 14A-14C illustrate top views of intermediate stages in themanufacture of another semiconductor structure having vertical andhorizontal gate structures in a high density layout. Similar to thestructure and techniques described above, FIG. 14A illustrates a topview of a gate structure 70 including vertical gate structures 70 a and70 b and horizontal gate structure 70 c. Portions of vertical gatestructures 70 a and 70 b are formed over active regions 72 and 74.Horizontal gate structure 70 c is formed over an insulating regionbetween active regions 72 and 74. Dummy patterns (not shown) may also beformed in active and insulating regions. The dummy patterns may haveuniform or non-uniform spacing and may be comprised of the same materialas the gate structures. An example method for forming gate structure 70and dummy patterns has been described above with reference to FIGS. 3through 5 and will not be repeated in the present embodiment. However,various layer deposition, photolithography, and etch techniques may beused to form gate structure 70. As will be noticed, vertical gatestructures 70 a, 70 b and horizontal gate structure 70 c form severalsections of an “H” shaped gate structure 70. It will be further noticedthat vertical gate structures 70 a, 70 b and horizontal gate structure70 c can form several “T” shaped parts of the gate structure 70. Forexample, in this embodiment, vertical gate structures 70 a and 70 b withhorizontal gate structure 70 c each form a respective “T” shaped part ofgate structure 70. In this embodiment, the horizontal gate structure 70c and vertical gate structure 70 a are interconnected by aninterconnection portion 75 a, and the horizontal gate structure 70 c andvertical gate structure 70 b are interconnected by an interconnectionportion 75 b, which will be later etched as further described below.Although these interconnection portions 75 a, 75 b are described in thisembodiment, gate structure 70 may be considered to have aninterconnection portion at any section between a horizontal gatestructure and a vertical gate structure which is desired to be etched.

FIG. 14B illustrates a photoresist 76 formed over gate structure 70protecting the vertical and horizontal gate structures but exposing theinterconnection portions 75 a, 75 b through a photoresist gap 78 a, 7 bin the photoresist 76. Similar to the previously discussed embodiment,photoresist 76 may extend beyond parts of gate structure 70 for betweenabout 10 nm and about 150 nm so that parts of the gate structure arecompletely covered. Gaps 78 a, 78 b are formed in the photoresist 76over the interconnection portions 75 a, 75 b. In one embodiment, gaps 78a, 78 b each have a width “y” between about 65 nm and about 95 nm (asshown by gate gaps 79 a, 79 b in gate structure 70 in FIG. 14C),although the width of photoresist gaps 78 a, 78 b are a designconsideration and can be changed according to the layout. In order toprevent over-etching through the photoresist gaps 78 a, 78 b in thesubsequent process steps causing gate ends to recess back into activeregion 72, 74 photoresist 76 extends beyond active regions 72, 74 for adistance between about 40 nm and about 60 nm (as shown by endcaps 77 a,77 b in FIG. 14C). The patterned photoresist 76 may be formed byphotolithography, immersion lithography, ion-beam writing, or othersuitable techniques. For example, the photolithography process mayinclude spin-coating, soft-baking, exposure, post-baking, developing,rinsing, drying, and other suitable processes.

Dummy patterns are then etched and photoresist 76 is removed. Theresulting gate structure after the photoresist 76 is removed isillustrated in FIG. 14C. The interconnection portions 75 a, 75 bunprotected by the photoresist 76 are also etched and removed, therebyforming endcaps 77 a, 77 b which each extend a minimum distance “z”between about 40 nm and about 60 nm above active regions 72, 74,respectively, and forming gate gaps 79 a, 79 b having a minimum width ybetween about 65 nm and about 95 nm. Thus, a distance x between a topedge of the horizontal gate structure 70 c and a bottom edge of activeregion 72 of the substrate is between about 105 nm and about 155 nm, anda distance between a bottom edge of the horizontal gate structure 70 cand a top edge of active region 74 of the substrate is between about 105nm and about 155 nm, which is reduced from the conventional spacingrequirement of 180 nm. Furthermore, a distance w between opposing edgesof the first and second active regions 72, 74 is between about 300 nmand about 400 nm. By using this embodiment of the present invention, theminimum extension of endcaps and the minimum spacing between verticaland horizontal gate lines are controlled and optimized to reduce thearea constraints conventionally required of vertical and horizontal gatelines, thus improving gate line density while also improving deviceperformance and leakage uniformity control.

The dummy patterns and the interconnection portion may be removed by adry etching, wet etching, or combination dry and wet etching process.For example, a wet etching process may include exposure to a hydroxidecontaining solution (e.g., ammonium hydroxide), de-ionized water, and/orother suitable etchant solutions. Etching the poly layer may beperformed using HBr, CF₄, Cl₂, O₂ or HeO₂ at a temperature of about 0°C.-100° C. Furthermore, the dummy patterns and the interconnectionportion may be removed in a single-step etching process or multiple-stepetching process. It is understood that other etching chemicals may beused for selectively removing the dummy dielectric and dummy poly gate.

The remaining elements of the MOS device such as spacers, source/drain,etc, are then formed. The forming process has been discussed in previousembodiments and thus will not be repeated.

FIGS. 15 and 16 illustrate top views of a conventional semiconductorstructure 80 and a semiconductor structure 90 having vertical andhorizontal gate structures in a high density layout in accordance withaspects of the present disclosure, respectively. Conventional structure80 includes vertical gate structures 80 a and 80 b and horizontal gatestructures 80 c and 80 d. Portions of vertical gate structures 80 a and80 b are formed over active regions 82 and 84. Horizontal gatestructures 80 c and 80 d are formed over insulating regions. Verticalgate structure 80 a includes an endcap 87 extending a minimum distanceof about 80 nm above active region 82, and a gate gap between a tip ofendcap 87 and horizontal gate structure 80 c is a minimum distance ofabout 100 nm. Thus, a conventional spacing requirement between a bottomedge of the horizontal gate structure 80 c and a top edge of activeregion 82 is about 180 nm.

In contrast, inventive structure 90 of FIG. 16 includes vertical gatestructures 90 a and 90 b and horizontal gate structures 90 c and 90 d.Portions of vertical gate structures 90 a and 90 b are formed overactive regions 92 and 94. Horizontal gate structures 90 c and 90 d areformed over insulating regions. Vertical gate structure 90 a includes anendcap 97 extending a minimum distance between about 40 nm and about 60nm above active region 92, and a gate gap between a tip of endcap 97 andhorizontal gate structure 90 c is a minimum distance between about 65 nmand about 95 nm, as shown by gate cut region 96. Thus, a greatly reducedspacing requirement of the present disclosure between a bottom edge ofthe horizontal gate structure 90 c and a top edge of active region 92 isbetween about 105 nm and about 155 nm as compared to the conventional180 nm.

FIGS. 17 and 18 illustrate top views of another conventionalsemiconductor structure and another semiconductor structure havingvertical and horizontal gate structures in accordance with aspects ofthe present disclosure, respectively. Conventional structure 100includes vertical gate structures 100 a, 100 b, 100 c, and a horizontalgate structure 100 c. Portions of vertical gate structures 100 a, 100 b,100 c are formed over active regions 102 and 104. Horizontal gatestructure 100 c is formed over an insulating region between activeregions 102 and 104. Vertical gate structures 100 a and 100 c eachincludes an endcap 107 a and 107 b, respectively, extending a minimumdistance of about 80 nm beyond active regions 102 and 104, respectively.Gate gaps between a tip of endcaps 107 a, 107 b and an opposing edge ofhorizontal gate structure 100 c is a minimum distance of about 100 nm.Thus, a conventional spacing requirement between an opposing edge of thehorizontal gate structure 100 c and an opposing edge of active region102 or 104 is about 180 nm.

In contrast, inventive structure 110 of FIG. 18 includes vertical gatestructures 110 a and 110 b and a horizontal gate structure 110 c.Portions of vertical gate structures 110 a and 110 b are formed overactive regions 112 and 114. Horizontal gate structure 110 c is formedover an insulating region between active regions 112 and 114. Verticalgate structures 110 a and 110 b each includes an endcap 117 a and 117 b,respectively, extending a minimum distance between about 40 nm and about60 nm beyond active region 112 and 114, respectively. A gate gap betweena tip of endcap 117 a or 117 b and an opposing edge of horizontal gatestructure 110 c is a minimum distance between about 65 nm and about 95nm, as shown by gate cut region 116 a, 116 b. Thus, a significantlyreduced spacing requirement of the present disclosure between anopposing edge of the horizontal gate structure 110 c and an opposingedge of active region 112 or 114 is between about 105 nm and 155 nm ascompared to the conventional 180 nm. Furthermore, a distance betweenopposing edges of the first and second active regions 112 and 114 isbetween about 300 nm and about 400 nm, whereas the comparable distancebetween opposing edges of the first and second active regions 102 and104 in the conventional structure is about 420 nm.

Thus, by using the embodiments of the present invention, the minimumextension of endcaps and the minimum spacing between vertical andhorizontal gate lines are controlled and optimized to reduce the areaconstraints conventionally required of vertical and horizontal gatelines, thus improving gate line density while also improving deviceperformance and leakage uniformity control.

Furthermore, FIGS. 19 and 20 illustrate top views of the conventionalsemiconductor structure 100 and a semiconductor structure 110 inaccordance with aspects of the present disclosure, respectively. As canbe seen, a contact 109 on the conventional gate structure 110 may havehigh contact resistance or open contact issues when landing a contact onthe structure 110. In contrast, the present disclosure provides a robustprocess for contact landing, as shown by a comparable contact 119 landedon innovative structure 110, which includes a larger horizontal gatestructure than the conventional horizontal gate structure (i.e., 90 nmwidth versus 60 nm width of comparable horizontal gate structures).

Referring now to FIG. 21, a flowchart illustrates a method offabricating a semiconductor structure with a high density gate layoutaccording to various aspects of the present disclosure. The method 200begins with block 202 in which a substrate and a gate dielectric layerover the substrate are provided. The method 200 continues with block 204in which a gate electrode layer is provided over the gate dielectriclayer. The gate electrode layer and the gate dielectric layer are thenetched to form a horizontal gate structure and a vertical gatestructure, as shown in block 206. The horizontal gate structure and thevertical gate structure are interconnected by an interconnectionportion. The method continues with block 208 in which a photoresist isformed to cover the horizontal gate structure and the vertical gatestructure and exposing the interconnection portion. Finally, theinterconnection portion is etched through the photoresist, as shown inblock 210.

It should be noted that the techniques and processes, such asphotoresist formation and etching, as disclosed above with reference toFIGS. 3-12 can also be implemented in the various embodiments disclosedabove with reference to FIGS. 13A-21. Conversely, it should be notedthat the techniques and processes as disclosed above with reference toFIGS. 13A-21 can also be implemented in the various embodimentsdisclosed above with reference to FIGS. 3-12. It is also understood thatthe semiconductor device may undergo further processing to form variousfeatures such as contacts/vias, interconnect metal layers, interlayerdielectric, passivation layers, inductors, capacitors, etc. before orafter the method outlined in FIG. 21.

The present disclosure provides for many different embodiments. One ofthe broader forms of the present disclosure involves a method offabricating a semiconductor device. The method includes forming a gatedielectric layer over a substrate, forming a gate electrode layer overthe gate dielectric layer, and etching the gate electrode layer and thegate dielectric layer to form a horizontal gate structure and a verticalgate structure, wherein the horizontal gate structure and the verticalgate structure are connected by an interconnection portion. The methodfurther includes forming a photoresist covering the horizontal gatestructure and the vertical gate structure, with the photoresist having agap exposing the interconnection portion between the horizontal gatestructure and the vertical gate structure, and then etching theinterconnection portion.

Another of the broader forms of the present disclosure involves anothermethod of fabricating a semiconductor device. The method includesproviding a semiconductor substrate comprising: a first active region; asecond active region; and an insulating region separating the first andthe second active regions. The method further includes forming avertical gate structure extending over the first and the second activeregions and the insulating region, and forming a horizontal gatestructure extending over the insulating region between the first and thesecond active regions, wherein the horizontal gate structure and thevertical gate structure are connected by an interconnection portion. Aphotoresist having a first portion and a second portion is then formed,wherein the first portion of the photoresist covers a portion of thevertical gate structure, and the second portion of the photoresistcovers the horizontal gate structure, wherein the first and the secondportions of the photoresist have a gap exposing the interconnectionportion directly over the insulating region. The interconnection portionis then etched.

Another of the broader forms of the present disclosure involves asemiconductor structure. The semiconductor structure includes asubstrate having a first active region, a second active region, and aninsulating region separating the first and the second active regions.The structure further includes a vertical gate structure extending overthe first and the second active regions and the insulating region, and ahorizontal gate structure extending over the insulating region betweenthe first and the second active regions, wherein the horizontal gatestructure and the vertical gate structure have a gap of about 65 nm andabout 95 nm therebetween directly over the insulating region.

Although the present invention and its advantages have been described indetail, it should be understood that various changes, substitutions andalterations can be made herein without departing from the spirit andscope of the invention as defined by the appended claims. Moreover, thescope of the present application is not intended to be limited to theparticular embodiments of the process, machine, manufacture, andcomposition of matter, means, methods and steps described in thespecification. As one of ordinary skill in the art will readilyappreciate from the disclosure of the present invention, processes,machines, manufacture, compositions of matter, means, methods, or steps,presently existing or later to be developed, that perform substantiallythe same function or achieve substantially the same result as thecorresponding embodiments described herein may be utilized according tothe present invention. Accordingly, the appended claims are intended toinclude within their scope such processes, machines, manufacture,compositions of matter, means, methods, or steps.

The foregoing has outlined features of several embodiments so that thoseskilled in the art may better understand the detailed description thatfollows. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A semiconductor structure, comprising: asubstrate having a first active region, a second active region, and aninsulating region separating the first and the second active regions; avertical gate structure extending over the first and the second activeregions and the insulating region; a horizontal gate structure extendingover the insulating region between the first and the second activeregions, wherein the horizontal gate structure and the vertical gatestructure have a gap of about 65 nm to about 95 nm therebetween directlyover the insulating region.
 2. The structure of claim 1, wherein thefirst and the second active regions are parallel, and wherein thevertical gate structure is a straight strip having a longitudinaldirection perpendicular to a longitudinal direction of the first and thesecond active regions.
 3. The structure of claim 1, wherein a distancebetween opposing edges of the first and second active regions is betweenabout 300 nm and about 400 nm.
 4. The structure of claim 1, wherein thehorizontal gate structure and the vertical gate structure form a T shapeor an L shape.
 5. The structure of claim 1, wherein an endcap of thevertical gate structure extends about 50 nm from an edge of an activeregion of the substrate, and wherein a distance between an edge of thehorizontal gate structure and an edge of an active region of thesubstrate is between about 105 nm and about 155 nm.
 6. The structure ofclaim 1, further comprising dummy patterns in an active region of thesubstrate, the dummy patterns having non-uniform spacing and beingcomprised of the same material as the gate structures.
 7. Asemiconductor structure, comprising: a first active region and a secondactive region in a substrate, the first active region and the secondactive region separated by an insulating region; a gate dielectric layerdisposed over the substrate; a gate electrode layer disposed over thegate dielectric layer; a horizontal gate structure extending over theinsulating region between the first active region and the second activeregion; and a first vertical gate structure and a second vertical gatestructure, the first vertical gate structure including an endcap,wherein the endcap extends between about 40 nm and about 60 nm from anedge of the first active region.
 8. The structure of claim 7, whereinthe horizontal gate structure and the first vertical gate structure forma T shape or an L shape.
 9. The structure of claim 7, wherein a distancebetween an edge of the horizontal gate structure and an edge of thefirst active region is between about 105 nm and about 155 nm.
 10. Thestructure of claim 7, wherein a distance between an edge of the firstaction region and an edge of the second active region is between about300 nm and 400 nm.
 11. The structure of claim 7, wherein the firstactive region and the second active region are parallel, wherein thefirst vertical gate structure has a longitudinal direction perpendicularto a longitudinal direction of the first active region, wherein thesecond vertical gate structure is has a longitudinal directionperpendicular to a longitudinal direction of the first active region.12. The structure of claim 7, wherein the second vertical gate structureincludes a second endcap, wherein the second endcap extends betweenabout 40 nm and about 60 nm from an edge of the second active region.13. The structure of claim 7, further including a first gap of about 65nm to about 95 nm over the insulating region, between the endcap and thehorizontal gate structure.
 14. The structure of claim 7, furtherincluding a second gap of about 65 nm to about 95 nm over the insulatingregion, between the second endcap and the horizontal gate structure. 15.A semiconductor structure comprising: a substrate having a first activeregion, a second active region that is parallel to the first activeregion, and an insulating region separating the first active region andthe second active region; a first vertical gate structure extending overthe first active region, the second active region and the insulatingregion; a second vertical gate structure extending over the first activeregion, the second active region and the insulating region, wherein thesecond vertical gate structure is parallel to the first vertical gatestructure; a first horizontal gate structure extending over theinsulating region between the first active region and the second activeregion, the first horizontal gate structure coupling the first verticalgate structure and the second vertical gate structure; and a secondhorizontal gate structure, wherein the first active region is betweenthe second horizontal gate structure and the first horizontal gatestructure, wherein there is a gap of about 65 nm to about 95 nm betweenthe second horizontal gate structure and the first vertical gatestructure.
 16. The structure of claim 15, further comprising: an endcapportion of the first vertical gate structure, wherein the endcap extendsin the direction of the second horizontal gate structure, wherein theendcap extends between about 40 nm and about 60 nm from an edge of thefirst active region.
 17. The structure of claim 15, wherein the secondhorizontal portion is spaced from the first active region by no greaterthan 155 nm.
 18. The structure of claim 15, wherein the secondhorizontal portion is coupled with the second vertical portion by acurved portion.
 19. The structure of claim 15, wherein the secondhorizontal portion is spaced from the first active region by about 105nm to about 155 nm.
 20. The structure of claim 15, wherein the firstvertical gate structure has a longitudinal direction perpendicular to alongitudinal direction of the first active region, wherein the secondvertical gate structure is has a longitudinal direction perpendicular toa longitudinal direction of the first active region.